1. Field of the Invention
Embodiments of the present invention relate to a monitor circuit, a bus system, and a bus bridge, which may be used as a bus system whose storage unit is shared by a plurality of masters.
2. Description of the Related Art
Conventionally, when a plurality of masters uses a main storage unit as a shared memory, it is frequently performed that a first master writes data into the shared memory and then a second master reads the data therefrom.
When the second master reads from the shared memory the data written by the first master thereto, before the second master starts a reading operation, it needs to be guaranteed that the first master has completed writing the data into the shared memory. A technique for ensuring such data writing is discussed in Japanese Patent Application Laid-Open No. 7-210500.
FIG. 6 illustrates an example of a configuration of a conventional bus system.
In the bus system illustrated in FIG. 6, an operation will be performed as below in which a master 901 writes data into a shared memory 903, and then a master 902 reads the data therefrom.
The master 901 writes the data into the shared memory 903 via a bus 904, a bus bridge 900, and a bus 905. At this point, when completing writing (transfer) the data into the bus bridge 900, the master 901 asserts a transfer completion signal.
Upon receiving the data written by the master 901 with a transfer control circuit 910, the bus bridge 900 starts writing the data into the shared memory 903 via the bus 905. A transfer monitor circuit 930 monitors the transfer control circuit 910 writing the data into the shared memory 903, and when the transfer control circuit 910 completes writing the data, the transfer monitor circuit 930 notifies an interruption control circuit 920 of transfer completion.
The transfer completion signal has been input from the master 901 to the interruption control circuit 920, and when the transfer completion signal is asserted, the interruption signal is output from the interruption control circuit 920 to the master 902. However, the interruption control circuit 920 masks the interruption signal to the master 902 until receiving the transfer completion notice from the transfer monitor circuit 930, and, upon receiving the transfer completion notice from the transfer monitor circuit 930, cancels masking of the interruption signal to the master 902.
When the interruption signal from the bus bridge 900 is asserted, the master 902 starts reading the data from the shared memory 903. At this point, the master 901 has completed writing the data into the shared memory 903.
As described above, the master 902 is controlled not to be activated until it is confirmed that the transfer to the shared memory 903 is issued in the bus bridge 900 so that consistency between writing data and reading data is guaranteed.
However, the above-described example of a conventional bus system includes one master which accesses the bus bridge 900. When the number of masters is increased, the interruption control circuit 920 included in the bus bridge 900 needs to be changed according to the number of masters. In other words, the bus bridge of the conventional bus system illustrated in FIG. 6 is not sufficiently flexible for being diverted into various types of bus systems.